1. Field of the Invention
The present invention relates to a semiconductor device and a method of operating the semiconductor device, and more particularly to a semiconductor memory device including a memory cell array and a method of operating the semiconductor memory device.
2. Description of the Related Art
Generally, a flash memory device applies a program voltage to a word line when programming a memory cell. Accordingly, the same program voltage is applied to memory cells connected to the same word line. In the memory cells connected to the same word line, program cells and program inhibition cells may coexist. The program cells and the program inhibition cells have the same voltage applied to the word line, but the program and inhibition cells are discriminated by a type of voltage applied to a bit line. For example, a ground voltage is applied to the bit line of the program cells, and a power voltage is applied to the bit line of the program inhibition cells. In order to decrease a range of a threshold voltage distribution in a program state, gradationally increased program pulses with a predetermined step are applied to the word line. As a result, a threshold voltage of each memory cell is gradationally increased, to reach a target program state.
FIG. 1 is a graph illustrating movement of threshold voltages of program memory cells according to a program method in the related art.
Referring to FIG. 1, gradationally increased program pulses with predetermined program voltage increments are applied to a word line of a selected memory cell. This is referred to as an Incremental Step Pulse Program (ISPP) method. In the process of being programmed from an erase state E to a target program state P1, the selected memory cell may temporarily have a threshold voltage Vth larger than a first verification voltage PV1a and smaller than a second verification voltage PV1b. That is, the selected memory cell has a threshold voltage distribution corresponding to a temporal program state T at a certain time point. A bit line voltage VBL applied to a bit line is maintained as 0V until the threshold voltage Vth of the selected memory cell reaches the first verification voltage PV1a, but when the threshold voltage Vth of the selected memory cell becomes larger than the first verification voltage PV1a, the bit line voltage VBL applied to the bit line is changed to XV, and the bit line voltage is maintained as XV until the threshold voltage Vth of the selected memory cell reaches the second verification voltage PV1b. When threshold voltage Vth of the selected memory cell becomes larger than the second verification voltage PV1b in response to progress of the program operation, a power voltage Vcc is applied to the bit line such that the selected memory cell is in a program completed state and thus is not programmed any more. When the threshold voltage Vth is larger than the first verification voltage PV1a and smaller than the second verification voltage PV1b, the bit line voltage VBL applied to the bit line is a constant XV regardless of the threshold voltage Vth. Accordingly, degrees of increase of the threshold voltages at point a, point b, and point c are the same, so that the threshold voltages move to point a′, point b′, and point c′. That is, the bit line voltage VBL applied to the memory cell having the threshold voltage at point c is the same as the bit line voltage VBL applied to the memory cell having the threshold voltage at point a. Such a program method in the related art makes it difficult to form a narrow threshold voltage distribution of the target program state P1.